LSI testing solutionProduct

Design and test environment construction tool compatible with STIL



It is a tool to build a design / test environment (design kit) compatible with international standard test description language STIL

Reduced test development TAT with STIL

In the conventional test development, the description method of test data is different in each step of test design, design verification, test program creation, test, failure analysis, and the description method of test data is different, conversion of test data and test information between steps, It was necessary to master. If there is a conversion error or backtracking, the TAT will increase. Depending on the test description language, there are restrictions on timing and pattern description, and it takes time and labor.

Therefore, by constructing a test environment based on STIL, by handling all test data in STIL, data conversion work in each process is eliminated. Since it is possible to use test vectors of STIL description generated from ATPG test generation tool and simulator and supplied from IP vendor, efficient test vector creation and test design become possible, shortening the test development period, reducing test cost You can reduce it.

Plug-in to an existing system as an open system

In addition, since it is provided as an open system, it is easy to plug into the customer's environment, and it is a system that can customize according to various environments using the access interface. With STIL Director, you can build your STIL-based test environment quickly, cheaply and reliably.

Structure of STILDirector

STIL parser

Load STIL files such as STIL, function vector and IP test vector created by the test vector generation tool into the STIL database of STILDirector. Check violations of the language specification of STIL data.

STIL generator

Generate an STIL file from the data read into the STIL database from the simulator output result etc.

Simulator interface

Generate simulation input file from STIL database. Simulation can be executed again with input vector data with tester rule check as input. Also, it divides (simulates) the simulation result into cycles and imports it into the STIL database. Furthermore, we extract the DC measurement address based on the simulation result.

Tester rule check

It can be checked beforehand whether it can be executed with a tester.

Access interface

You can create user application programs that match the existing environment using the application programming interface that reads and writes data from the STIL database.

Tester interface

Test data for tester generation is possible.

Fault simulator interface

Generate input file for fault simulator.

Features of STILDirector

Interface with STIL data

  • You can read and output STIL data
  • You can check violations of STIL's language specifications

STIL output by readable ATPG tool

  • Synopsys TetraMAX
  • Mentor FastScan
  • Cadence TestBench/Encounter

Interface with simulator

  • You can generate inputs for various simulators
  • You can enter the results file of various simulators
  • Simulation results can be analyzed
  • Automatically extract expected values from simulation results and create STIL file
  • DC measurement address is automatically extracted

Supporting simulator

  • Verilog-XL
  • NC-Verilog
  • NC-SIM
  • ModelSim
  • VCS

Interface with tester

  • You can check whether it is a pattern description that can be used by the tester before executing the tester
  • Simulation results can be cycled

Test pattern generation tester

  • Advantewst T33xx, T66xx
  • Teradyne J921, J971

Interface with existing system

It is an open system configuration that can be plugged into the user's environment It can be customized by combining with the database access interface

Supported platforms

  • Linux / Intel PC
  • Sun Solaris / Sun Sparc
  • HP-UX / HP9000 Series


STILDirector works on engineering workstation, PC