Solstice-TDS Automatic EVCD to ATE Vector Translation: TimeTable

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While translating ATPG patterns (WGL and STIL formats) is a push-button operation using Solstice-TDS, converting Verilog simulation output (VCD and EVCD) to a tester format involves a process called cyclization. This process creates cycle-based timing from the event-based VCD/EVCD file. With Solstice TimeTable, signals, directions, test period, per-pin timing, and ATE format are all automatically […]

LSI testing solution

World Leading Enterprise Strength Vector Translation Platform Since 1979

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Largest Installed BaseSince 1979, Solstice-TDS has been used by generations of test engineers.  Solstice-TDS established many standard formats and methodoglies.  WGL was Solstice-TDS’s contribution to the industry, and has been used as the primary standard test interface language by ATPG tools before STIL.  Flow-based conversion methodology has been standardized in many top electronics firms.Supported EDA […]

Design solution

Pre-Silicon Test Pattern Validation, Debug, and Re-target Solution

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Solstice-PV helps design and test teams to work in the same environment, using waveforms as the universal communication language.Scan and functional patterns (ATPG, BIST, STIL, WGL, various ATE formats), including those from IP-core vendors, can be validated with the designer’s DUT model for advanced preparation of test patterns, and more importantly, to perform early detection […]